Hello-FPGA-FMC-QSFP-X2
● Memory: 24LC04 I2C EEPROM
● QSFP+: 2 ports ×4 differential pairs, 25Gbps per lane, total 200Gbps bandwidth
● Test Tools: IBERT BER test, eye diagram scanning
● Compatibility: QSFP+ modules (SR4/LR4/PSM4), DAC copper cables and AOC fiber cables
Hello-FPGA-FMC-QSFP-X2
Dual QSFP+ 100G Optical FMC Daughter Card - VITA 57.1 Compliant | 100Gb/s Aggregate Bandwidth | Dual High-Speed Interfaces
4 Core Advantages
Full Standard Compliance
Fully compliant with VITA 57.1 standard, equipped with FMC HPC high-density 400-pin connector (Model: ASP-134488-01). It supports adjustable VADJ voltage (1.2V/1.8V/2.5V), compatible with most mainstream FPGA carrier boards and maximizes carrier board reusability.
Dual 100G High-Speed Interfaces
Integrated 2 independent QSFP+ optical transceivers. Each port contains 4 pairs of differential transmit/receive lanes (Lane 0~3) with 25Gbps per lane. The aggregate bandwidth reaches up to 200Gb/s. It also supports 40G→4×10G breakout function to meet ultra-high bandwidth transmission requirements.
Professional Test Compatibility
Fully compatible with Xilinx VIVADO development environment, supporting professional debugging tools including IBERT BER test, eye diagram scanning and jitter analysis. The target bit error rate is as low as 1.24×10⁻¹¹, ensuring high accuracy and reliability for high-speed signal transmission verification.
Flexible Expansion & Upgrade
Compatible with QSFP+ optical modules (SR4/LR4/PSM4), passive/active DAC cables and Active Optical Cables (AOC). The transmission distance ranges from 1m to 100m. Hot-swap supported, which allows maintenance and upgrade without system shutdown for various deployment scenarios.
Product Introduction
- Hello-FPGA-FMC-QSFP-X2 is a VITA 57.1 compliant dual 40/100G high-speed optical FMC daughter card with FMC HPC interface, specially designed for FPGA development, high-speed data transmission verification and data center interconnection.
- Each port is equipped with 4 transmit & receive lanes, delivering up to 100Gb/s bandwidth. 2 on-board 156.25MHz high-precision oscillators provide stable clock for precise timing. Integrated 24LC04 I²C EEPROM stores board ID & manufacturer info to enable automatic module detection.
- With high bandwidth, broad compatibility and easy operation, it supports hot-swap optical modules and multiple cable types. It acts as core adapter hardware for high-end network & embedded systems, widely used in intelligent vehicles, medical imaging, aerospace and industrial automation.
- As an efficient FPGA I/O expansion card, it eliminates complicated protocol development, reduces system power consumption & BOM cost, and shortens project development cycle significantly.
Hardware Features
- Compliance: Fully follow VITA 57.1, adopt FMC HPC 400-pin connector (ASP-134488-01) with stable cross-brand compatibility.
- Interfaces: Dual QSFP+ transceivers, 4 differential TX/RX lanes per port, 25Gbps per lane, max 100Gb/s per port.
- Clock & Storage: Dual 156.25MHz high-precision oscillators; 24LC04 I²C EEPROM for automatic board identification.
- Module Compatibility: QSFP+ SR4/LR4/PSM4 optical modules, 1-7m DAC copper cables, 10-100m AOC active optical cables; support hot-swap & 40G→4×10G breakout.
- Power Input: +3.3V, +12V from carrier board; adjustable VADJ (1.2V/1.8V/2.5V) for different I/O voltage standards.
- Software Support: Native compatible with Xilinx VIVADO, support IBERT BER test, eye diagram scan & jitter analysis.
- Core Functions: Hot-swap, I²C auto-detection, high-speed signal integrity test, multi-module compatibility, 40G breakout.
GTY High-Speed Transceiver Measured Eye Diagram
Signal integrity test on FPGA GTY high-speed serial transceivers with this dual QSFP FMC card. 25Gbps transmission test under standard PRBS-31 pattern. The eye diagram shows wide opening margin and stable long-distance high-speed performance.
Matching Card: Hello-FPGA-FMC-QSFP-X2 | Test Pattern: PRBS-31 | Per Lane Rate: 25Gbps
Technical Specifications
| Category | Detailed Specifications |
|---|---|
| Basic Info | Product Name: Hello-FPGA-FMC-QSFP-X2; Compliance Standard: VITA 57.1 |
| Interface Spec | Type: FMC HPC; Connector: ASP-134488-01; Pin Count: 400 |
| Signal & Rate | Dual QSFP+ ports, 4 differential lanes each; Max per port bandwidth: 100Gb/s; Single lane rate:25Gbps |
| On-board Components | 2×156.25MHz oscillators; 24LC04 I²C EEPROM |
| Supported Modules | SR4/LR4/PSM4 optics, 1-7m DAC, 10-100m AOC; 40G→4×10G breakout |
| Test Performance | Tools: Xilinx IBERT, eye diagram & jitter analysis; Target BER ≈1.24×10⁻¹¹ |
| Power Supply | +3.3V, +12V, adjustable VADJ 1.2/1.8/2.5V |
| Software Environment | Xilinx VIVADO; IBERT, ILA signal capture |
| Core Functions | Hot-swap, I²C auto detection, high-speed signal test, breakout mode |
| Mechanical Size | Standard FMC daughter card dimension |
Product Dimension Drawing
Standard FMC Daughter Card Dimensions (Unit: mm)
Safety Warnings (Must Read)
- Never hot-plug the board: Power off carrier board & disconnect power cord before install/removal. Live plugging will permanently damage the card or carrier board.
- Mandatory ESD protection: Release static electricity before touching PCB components. Anti-static wrist strap recommended. Static destroys precision chips.
- Module Installation: Insert QSFP modules gently until locked; avoid forced plug/unplug. Hot-swap only under idle system status.
- Power Safety: Follow carrier voltage specs strictly; prevent overvoltage & reverse polarity to avoid circuit burnout.
- Environment: Do not store/operate under water splash, direct sunlight, strong EM field, heavy vibration or dust for long-term stable operation.
Quick Start Guide
- Hardware Install: Plug Hello-FPGA-FMC-QSFP-X2 into FMC HPC slot, fasten screws; insert QSFP optical/DAC/AOC modules firmly.
- Power Setup: Confirm carrier board stable power; set VADJ voltage (1.2/1.8/2.5V) based on I/O standard.
- Software Config: Open Xilinx VIVADO, load board constraint files, configure clock & rate parameters, enable 40G breakout if needed.
- Test & Verify: Run IBERT BER test & eye diagram scan, confirm link stable with BER ≤1.24×10⁻¹¹.
- System Integration: Mount the card & cables with good heat dissipation after passing test.
- Maintenance: QSFP modules support hot-swap, no full system power-off required for replacement.
Typical Application Scenarios
