Hello-FPGA-FMC-QSFP-X2
● Memory: 24LC04 I2C EEPROM
● QSFP+: 2 ports ×4 differential pairs, 25Gbps per lane, total 200Gbps bandwidth
● Test Tools: IBERT BER test, eye diagram scanning
● Compatibility: QSFP+ modules (SR4/LR4/PSM4), DAC copper cables and AOC fiber cables
Hello-FPGA-FMC-QSFP-X2
Dual QSFP+ 100G Optical FMC Daughter Card - VITA 57.1 Compliant | 100Gb/s Aggregate Bandwidth | Dual High-Speed Interfaces
4 Core Advantages
Full Standard Compliance
Fully compliant with VITA 57.1 standard, equipped with FMC HPC high-density 400-pin connector (Model: ASP-134488-01). It supports adjustable VADJ voltage (1.2V/1.8V/2.5V), compatible with most mainstream FPGA carrier boards and maximizes carrier board reusability.
Dual 100G High-Speed Interfaces
Integrated 2 independent QSFP+ optical transceivers. Each port contains 4 pairs of differential transmit/receive lanes (Lane 0~3) with 25Gbps per lane. The aggregate bandwidth reaches up to 200Gb/s. It also supports 40G → 4×10G breakout function to meet ultra-high bandwidth transmission requirements.
Professional Test Compatibility
Fully compatible with Xilinx VIVADO development environment, supporting professional debugging tools including IBERT BER test, eye diagram scanning and jitter analysis. The target bit error rate is as low as 1.24×10⁻¹¹, ensuring high accuracy and reliability for high-speed signal verification.
Flexible Expansion & Upgrade
Compatible with QSFP+ optical modules (SR4/LR4/PSM4), passive/active DAC cables and Active Optical Cables (AOC). The transmission distance ranges from 1m to 100m. Hot-swap supported, which allows maintenance and upgrade without system shutdown for various deployment scenarios.
Product Introduction
- Hello-FPGA-FMC-QSFP-X2 is a VITA 57.1 compliant dual 40/100G high-speed optical FMC daughter card with FMC HPC interface. It is specially designed for FPGA development, high-speed data transmission verification and data center interconnection.
- Each port is equipped with 4 transmit and receive lanes, delivering a maximum bandwidth of 100Gb/s. 2 on-board 156.25MHz high-precision crystal oscillators provide stable clock signals for accurate timing. Integrated 24LC04 I²C EEPROM supports I²C protocol to store board ID, manufacturer info and realize automatic module detection.
- Featuring high bandwidth, full compatibility and easy operation, this board supports hot-swap for optical modules and works with various cables & modules. It is a core component for high-end network and embedded systems, widely used in intelligent vehicles, medical devices, aerospace, industrial automation and other fields.
- As an excellent FPGA I/O expansion module, it simplifies system design without requiring complex protocol knowledge, reduces power consumption and cost, shortens project cycle and improves FPGA development efficiency.
Hardware Features
- Compliance Standard: Strictly follow VITA 57.1 standard, adopt FMC HPC (High Pin Count) interface, connector model ASP-134488-01 with 400 pins for stable connection.
- Interface Configuration: 2 QSFP+ optical transceivers, each with 4 pairs of differential transmit/receive lanes (Lane 0~3). Max rate: 25Gbps per lane, aggregate bandwidth up to 100Gb/s.
- Clock & Storage: 2 on-board 156.25MHz high-precision crystal oscillators; 24LC04 I²C EEPROM for board information storage.
- Compatible Devices: QSFP+ optical modules (SR4/LR4/PSM4), QSFP+ DAC cables (1-7m), QSFP+ AOC cables (10-100m). Support hot-swap and 40G → 4×10G breakout function.
- Power Compatibility: Powered by carrier board with +3.3V, +12V and adjustable VADJ (1.2V/1.8V/2.5V) for different I/O voltage levels.
- Software Compatibility: Works with Xilinx VIVADO, supports IBERT BER test, eye diagram scanning and jitter analysis for development and testing.
- Core Functions: Hot-swap, I²C automatic module detection, high-speed signal verification, multi-type cable & module adaptation, 40G → 4×10G breakout.
GTY High-Speed Transceiver Measured Eye Diagram
Signal integrity test for FPGA GTY high-speed serial transceivers. Combined with this dual QSFP FMC daughter card to complete 25Gbps high-speed transmission test with standard PRBS-31 pseudo-random bit sequence. The measured eye diagram shows sufficient opening margin and excellent stability for high-speed long-distance transmission.
Matching Expansion Card: Hello-FPGA-FMC-QSFP-X2 | Test Sequence: PRBS-31 | Test Rate Per Lane: 25Gbps
Technical Specifications
| Category | Detailed Specifications |
|---|---|
| Basic Info | Product Name: Hello-FPGA-FMC-QSFP-X2 High-Speed Optical Module; Compliance Standard: VITA 57.1 |
| Interface Spec | Interface Type: FMC HPC (High Pin Count); Connector Model: ASP-134488-01; Pin Count: 400 Pins |
| Signal & Rate | QSFP+ Ports: 2 Ports, 4 differential lanes per port; Maximum transmission rate per channel: 100Gb/s; Test Rate Per Lane: 25Gbps |
| On-board Components | Crystal Oscillator: 2 × 156.25MHz High-Precision Oscillator; Storage Chip: 24LC04 I²C EEPROM |
| Compatible Modules | Optical Modules: QSFP+ SR4/LR4/PSM4; DAC Cables: 1-7m; AOC Cables: 10-100m; Support 40G → 4×10G Breakout |
| Test Performance | Supported Tools: Xilinx IBERT (BER Test, Eye Diagram Analysis); Target BER: ≈1.24×10⁻¹¹ |
| Power Supply | Supported Voltage: +3.3V, +12V, Adjustable VADJ (1.2V/1.8V/2.5V) |
| Core Functions | Hot-swap, I²C Module Detection, High-speed Signal Verification, Multi-cable/Module Compatibility, 40G → 4×10G Breakout |
| Software Compatibility | Development Environment: VIVADO; Debug Tools: IBERT (BER Test), Eye Diagram Scan, Jitter Analysis |
| Mechanical Dimensions | 83.05mm×76.5mm×69mm×62.98mm×54.6mm (Standard FMC Daughter Card Size) |
Product Dimension Drawing
Standard FMC Daughter Card Dimensions (Unit: mm)
Safety Warnings (Must Read)
- Do NOT plug or unplug the board while powered on. Power off the FPGA carrier board and disconnect power cord before installation or removal. Live operation may permanently damage the daughter card, carrier board or connected devices.
- ESD Protection Required: Discharge static electricity from your body before touching electronic components. Wearing an anti-static wrist strap is recommended. Static electricity will cause permanent damage to precision chips.
- Standard Module Installation: Insert QSFP+ modules/cables gently until fully locked. Forcible insertion or removal will damage the ports. Perform hot-swap only when the system is idle.
- Power Safety: Follow the power requirements of carrier board strictly. Ensure stable voltage within rated range to avoid circuit burnout caused by overvoltage or reverse polarity.
- Environmental Requirements: Do not store or use the product in areas with water splash, direct sunlight, strong electric/magnetic fields, severe vibration or heavy dust, to guarantee long-term stable operation.
Quick Start Guide
- Hardware Connection: Insert Hello-FPGA-FMC-QSFP-X2 into the FMC HPC slot of FPGA carrier board and tighten fixing screws. Install QSFP+ optical modules, DAC or AOC cables as required and ensure firm connection.
- Power Configuration: Confirm the carrier board is powered normally and stable. Set VADJ voltage (1.2V/1.8V/2.5V) according to I/O level requirements.
- Software Configuration: Launch Xilinx VIVADO, load board configuration files, set clock and data rate parameters. Enable 40G → 4×10G breakout function if needed.
- Test & Verification: Run IBERT tool to perform BER test and eye diagram scanning. Confirm link status is normal and BER meets the standard (≈1.24×10⁻¹¹).
- System Deployment: Deploy the device to target application scenario, fix cables and boards, ensure good heat dissipation and complete system integration.
- Maintenance & Upgrade: Hot-swap is supported for QSFP+ modules and cables. Direct replacement is available without shutting down the whole system.
Typical Application Scenarios
