PCIe-4005 Camera Link Camera Simulator

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    PCIe-4005 Camera Link simulator User Manual.pdf

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PCIe-4005 Camera Link Camera Simulator Product 

Product Introduction

The PCIe-4005 Camera Link Camera Simulator is a professional simulation tool designed for the development, testing and verification of vision systems. It can accurately simulate the working behavior of real Camera Link cameras and complete the full-process verification of image acquisition processes and data processing functions without relying on physical cameras. The product strictly complies with the Camera Link communication protocol standard, fully compatible with three transmission configuration modes of Base, Medium and Full, equipped with Xilinx FPGA core chip and 1GB DDR3 memory, supporting rich image source input, pixel format selection and trigger mode configuration. With a visual upper computer software, it provides a flexible, efficient and stable hardware simulation solution for R&D and testing in industrial vision, machine vision and other fields. It also supports secondary development to meet personalized simulation needs.

Four Core Advantages

1. Full Protocol Compatibility & Multi-Mode Adaptation：Strictly compliant with the Camera Link protocol, perfectly supporting Base/Medium/Full three transmission configurations, compatible with key control signals such as FVAL and LVAL, and adapting to the testing needs of vision systems with different resolutions and pixel formats.

2. Highly Flexible Configuration & Multi-Scene Coverage：Supporting three image transmission modes of default gradient map, custom gradient map and local image, providing 6 trigger modes such as software trigger, edge trigger and level trigger, combined with 3 transmission modes, it can flexibly adapt to various simulation test scenarios.

3. High-Performance Hardware & High-Stable Transmission：Adopting Xilinx XC7A100T FPGA chip, equipped with 1GB DDR3 memory and 3U PCIe Gen2x4 high-speed interface, dual SDR interfaces support high-speed image data transmission, and the onboard IO interface has ESD and overvoltage protection to ensure the stability and reliability of data transmission.

4. Visual Operation & Easy Secondary Development：Matching with Windows-based upper computer software, providing visual interfaces for file setting and parameter configuration, supporting configuration save/load; providing a complete SDK development kit and detailed manual, supporting API calls and Qt interface customization, reducing the threshold of secondary development.

Board Functions

Image Simulation and Control Function

• Support three image transmission modes: default gradient map, custom gradient map and local image. The custom gradient map supports a maximum ultra-high resolution of 50000×50000, and the local image is compatible with multiple formats such as BMP, JPEG, PNG, TIFF, bin/raw.

• Flexible configuration of image timing parameters (FVAL_Setup/Hold, LVAL_L/H, frame interval/line interval, etc.), supporting multiple pixel formats such as Mono8/10/12/14/16 and RGB8/10/12.

Trigger Control Function

Provide 6 trigger modes to meet different trigger requirements: software trigger (API command), rising edge trigger, falling edge trigger, high level trigger, low level trigger, immediate trigger (customizable internal trigger frequency).

 Transmission and Channel Function

• Support three Camera Link transmission modes of Base/Medium/Full, with throughput of 255MB/s, 510MB/s and 680MB/s respectively, adapting to vision systems with different bandwidths.

• Provide single-line (1Y) multi-channel geometric layout, supporting 1X1/1X2/1X3/1X4/1X8_1Y modes, which can set 1-8 pixels transmitted by a single pixel clock, flexibly adapting to the transmission logic of different cameras.

 Transmission and IO Control Function

• Support three output modes: finite frame, continuous transmission and continuous wrapping, adapting to simulation scenarios with different data volumes. The simulator can be started/stopped with one click and global reset through API.

• Equipped with dual SDR camera interfaces, D-SUB26 External IO, 26PIN INTERNAL I/O牛角header port, including differential IO, optocoupler isolated IO, LVDS/TTL interface, 24-way GPIO, supporting custom communication between boards and linkage with external devices.

 Secondary Development Function

Provide a complete SDK development kit, supporting API command calls to configure all parameters, the board hardware resources are open, matching with a detailed development manual, supporting Qt5/6 interface customization and function expansion.

Product Parameters

Mechanical Dimension Drawing

The board is designed in standard 3U PCIe industrial size, equipped with an air-cooled radiator, the overall size is compatible with PCIe standard slots, and the baffle size complies with the industrial 3U PCIe specification (refer to Figure 2-3 Baffle Size and Figure 2-2 PCIe4005 Structure Diagram in the product manual for specific dimensions); the main body of the board is a standard PCIe plug-in design, which can be directly inserted into the PCIe slot of industrial computer/server for easy installation.

Usage Method

 Hardware Installation

1. Confirm that the industrial computer/server supports PCIe Gen2x4 slot, turn off the device power and unplug the power cord;

2. Insert the PCIe-4005 board into the idle PCIe slot to ensure good contact of the gold finger, and tighten the baffle fixing screws;

3. Connect external IO devices (such as trigger signal source, image acquisition card) to the board's D-SUB26 or SDR interface, turn on the industrial computer power, and install the board's matching driver program.

Software Installation and Startup

1. Install the PCIe-4005 dedicated library file and upper computer software, supporting Windows 10/11 operating system;

2. If secondary development is required, install Qt5/6 development environment and import the matching SDK development kit;

3. Open the upper computer software, the software will automatically identify the board device and complete the device initialization.

 Parameter Configuration and Operation

1. File Setting Page: Select the data source type (local image/bin file), browse and select the file path, the image file can apply the size to the parameter configuration with one click of "Auto Apply", and the bin file needs to set the resolution and zero-filling method manually;

2. Parameter Setting Page:

• Select the data source (local image/hardware test chart), the hardware test chart can select horizontal/vertical/diagonal stripes;

• Configure device topology (1X1/1X2/1X4/1X8_1Y), pixel format, zero-filling method;

• Select trigger mode (software trigger/rising edge trigger/immediate trigger, etc.), transmission mode (finite frame/continuous transmission/continuous wrapping);

• Set timing parameters (FVAL_Setup/Hold, FVAL_L, LVAL_L), resolution (columns/rows), frame rate, running time (0 for infinite running);

3. Start Operation: After the parameter configuration is completed, click "Start Transmission". In software trigger mode, click "Software Trigger" to send a single frame of data, you can terminate the transmission through the "Stop" button, and restore the default configuration with "Reset Parameters";

4. Configuration Save/Load: After completing the parameter configuration, click "Save Configuration" to generate a configuration file, and the parameters can be quickly restored through "Load Configuration" later without repeated setting.

 Secondary Development Usage

1. Refer to the API command table in the product manual, call functions such as PCIe4005_Start/Stop to realize device control;

2. Configure core parameters such as image parameters, trigger mode and transmission mode through API to realize automatic simulation test;

3. Customize the personalized upper computer interface and expand functional modules based on Qt5/6 development environment.

Notes

1. Hardware Installation: Turn off the industrial computer power and unplug the power cord before installing/removing the board to avoid electrostatic breakdown of the chip, and wear an anti-static wristband during operation; ensure stable power supply of the PCIe slot, tighten the board baffle screws to prevent poor contact.

2. Interface Usage: The LVDS input of the External IO interface needs to be connected with a 100Ω termination resistor, the external trigger signal needs to match the board level to avoid damage to the interface due to overvoltage input; the INTERNAL I/O interface is 24-way GPIO directly connected to FPGA, confirm the wiring definition before use to prevent short circuit.

3. Parameter Configuration: The transmission mode and channel layout must be matched collaboratively during configuration, the Full mode currently only supports 1X8_1Y 8bit transmission mode; when sending local images, the resolution of all image files must be consistent, and the bin/raw format needs to set the resolution manually and accurately, otherwise the image data will be abnormal.

4. Software Usage: Ensure that the board driver and dedicated library file are installed successfully before the upper computer software runs, check the hardware connection and driver version when the device is not recognized; follow the SDK development specifications during secondary development to avoid device abnormalities caused by illegal API calls.

5. Heat Dissipation and Operation: The board adopts an air-cooled radiator, ensure good heat dissipation of the industrial computer chassis during operation to avoid device frequency reduction or crash caused by high temperature; if an abnormality occurs after long-term operation, the board can be restarted through the "Global Reset" function, or reinstalled after power off.

6. Data Transmission: Ensure sufficient memory of the industrial computer when transmitting high-resolution custom gradient maps to avoid data transmission interruption due to insufficient memory; the finite frame mode is suitable for scenarios where the data volume is less than the onboard DDR3 capacity, and continuous transmission/wrapping mode is recommended for large-quantity data simulation.

Application Fields

1. Machine Vision System R&D: Development and testing of camera acquisition cards and visual processing algorithms, completing the full-process R&D of image acquisition, data transmission and algorithm verification without physical cameras.

2. Industrial Vision Equipment Production Testing: Factory testing and fault troubleshooting of visual inspection equipment, industrial cameras and image acquisition cards, quickly verifying the compatibility and stability of equipment, and improving the efficiency of production testing.

3. Experiments in Universities/Research Institutions: Teaching experiments and scientific research projects for majors such as machine vision and digital image processing, providing a low-cost and highly flexible camera simulation experiment platform for students and researchers.

4. Vision System Maintenance and Debugging: On-site maintenance and fault debugging of industrial production line vision systems, quickly locating the fault points of acquisition cards, transmission lines and processing modules, and reducing the cost of on-site debugging.

5. Security Monitoring Equipment Testing: Functional testing of security monitoring cameras and video acquisition equipment, simulating image data of different resolutions and frame rates, and verifying the video acquisition and processing capabilities of the equipment.

6. Autonomous Driving Vision Module R&D: Development and testing of autonomous driving on-board vision acquisition systems, simulating image data of road scenes, and verifying the acquisition and recognition algorithms of vision modules.