CXP2.0 HOST FPGA IP
The CXP2.0 HOST FPGA IP is a high‑performance host IP core compliant with the CoaXPress V2.0 standard, providing high‑throughput image and control transmission for machine vision and industrial imaging systems.
CXP2.0 HOST FPGA IP
General Description
The CXP2.0 HOST FPGA IP is a high‑performance host IP core compliant with the CoaXPress V2.0 standard, providing high‑throughput image and control transmission for machine vision and industrial imaging systems.
Key Features
- Compliant with CoaXPress V2.0 (JIIA NIF‑001‑2019), backward compatible with CoaXPress V1.1 (JIIA NIF‑001‑2013) and V1.0 (JIIA NIF‑001‑2010).
- Supports high‑speed downlink up to CXP‑12 and 41.6 Mbps uplink low‑speed link; supports all link speeds defined in the CoaXPress specification.
- Supports link configurations of 1, 2, 4, 8 lanes to satisfy high‑throughput data transmission.
- Supports up to 8 parallel video streams, enabling one host to connect multiple cameras or multi‑sensor data from a single camera.
- Employs FPGA embedded high‑speed transceivers as the PHY layer for simplified implementation.
- User control bus: AXI4 interface.
- User data bus: dedicated video bus interface.
- Dedicated GPIO and trigger interface to send trigger signals to downstream devices.
Device Support
- Supports all Xilinx FPGA families.
- Currently validated development boards:
KC705, KCU105, ZCU102, ALINX Z19, ALINX Z7P, ALINX AXKU040, etc.
Diagrams
Figure 1: CXP2.0 HOST FPGA IP Data Flow Block Diagram
Figure 2: CXP Host FPGA IP (Xilinx IP Integrator)
