CXP2.0 HOST FPGA IP
●Protocol Standard: CoaXPress V2.0 (Backward compatible with V1.1, V1.0)
●Link Configuration: Supports 1/2/4/8 links, max. CXP‑12 mode
●Transmission Specs: High-speed downstream image transmission, 41.6Mbps uplink, up to 8 parallel video streams
●Interface Bus: AXI4 control bus, dedicated video bus, equipped with GPIO and trigger interfaces
●Hardware Compatibility: Supports all Xilinx FPGAs, verified on multiple development boards
●PHY Solution: Adopts FPGA built-in high-speed transceivers
●Link Configuration: Supports 1/2/4/8 links, max. CXP‑12 mode
●Transmission Specs: High-speed downstream image transmission, 41.6Mbps uplink, up to 8 parallel video streams
●Interface Bus: AXI4 control bus, dedicated video bus, equipped with GPIO and trigger interfaces
●Hardware Compatibility: Supports all Xilinx FPGAs, verified on multiple development boards
●PHY Solution: Adopts FPGA built-in high-speed transceivers
CXP2.0 HOST FPGA IP
Product Overview
CXP2.0 HOST FPGA IP is a high-performance host-side IP core compliant with the CoaXPress V2.0 standard. It provides high-throughput transmission of image data and control commands for machine vision and industrial imaging systems.
Key Features
- Compliant with CoaXPress V2.0 (JIIA NIF‑001‑2019), backward compatible with V1.1 and V1.0
- Supports maximum CXP‑12 high-speed downstream, with 41.6 Mbps low-speed upstream link
- Supports 1/2/4/8 lane configurations to meet high-bandwidth data transmission requirements
- Supports up to 8 parallel video streams, enabling a single host to connect multiple cameras or sensors
- Utilizes FPGA built-in high-speed transceivers as PHY layer for simple and reliable implementation
- User control bus: AXI4 Interface
- User data bus: Dedicated video bus interface
- Dedicated GPIO and trigger interface for sending trigger signals to downstream devices
Supported Devices
- Supports all Xilinx FPGA families
- Validated development boards: KC705, KCU105, ZCU102, ALINX Z19, Z7P, AXKU040, etc.
Product Block Diagram
CXP2.0 HOST FPGA IP Data Flow Diagram
CXP2.0 HOST IP Core Pin Definition Diagram
