CXP2.0 DEVICE FPGA IP
The CXP2.0 DEVICE FPGA IP is a high-performance intellectual property core designed to comply with the CoaXPress V2.0 standard, providing reliable and high-throughput data transmission capabilities for FPGA-based imaging and industrial control applications.
CXP2.0 DEVICE FPGA IP
Overview
The CXP2.0 DEVICE FPGA IP is a high-performance intellectual property core designed to comply with the CoaXPress V2.0 standard, providing reliable and high-throughput data transmission capabilities for FPGA-based imaging and industrial control applications.
Key Features
- Compliant with the CoaXPress V2.0 standard (JIIA NIF-001-2019), and backward compatible with CoaXPress V1.1 (JIIA NIF-001-2013) and V1.0 (JIIA NIF-001-2010) standards.
- Supports CXP-12 protocol, featuring a high-speed link with a maximum data rate of 12.5 Gbps and a low-speed link with a maximum data rate of 41.6 Mbps, supporting multiple link rate options.
- Supports multiple CoaXPress links, making it suitable for high-throughput application scenarios that require large-volume data transmission.
- Supports multiple video streams, enabling direct connection to multiple independent sensors or multi-channel imaging sensors.
- Supports up to 4 parallel CoaXPress links to further improve data transmission efficiency.
- Implements control channel operations through a simple burst local bus, eliminating the need for CPU intervention and reducing system resource occupation.
- Equipped with a highly configurable video stream interface, which can be directly connected to various types of imaging sensors without additional interface conversion modules.
- Integrated with a built-in CRC-32 generator and checker to ensure the integrity and reliability of data transmission.
Compatibility
The IP core supports all Xilinx FPGA product families. Currently adapted development boards include:
KC705, KCU105, ZCU102
Related Diagrams
Figure 1: CXP2.0 DEVICE FPGA IP Data Flow Block Diagram
