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CXP2.0 DEVICE FPGA IP

●Protocol Standard: CoaXPress V2.0 (Backward compatible with V1.1, V1.0)
●Link Configuration: Max. CXP‑12 mode, up to 4 parallel links
●Transmission Specs: 12.5Gbps high-speed link, 41.6Mbps uplink, supports multiple video streams
●Interface Features: Configurable video interface, simple local control bus, no CPU required
●Reliability: Built-in CRC-32 check to ensure data integrity
●Hardware Compatibility: Supports all Xilinx FPGAs, verified on multiple development boards

CXP2.0 DEVICE FPGA IP

Documentation Download

Hello-FPGA CoaXPress 2.0 Device FPGA Demo UserManual.pdf

Specifications

Product Overview

CXP2.0 DEVICE FPGA IP is a high-performance device-side IP core compliant with the CoaXPress V2.0 standard. It provides highly reliable and high-throughput data transmission capability for FPGA-based imaging equipment and industrial control applications.

Key Features

  • Compliant with CoaXPress V2.0 standard (JIIA NIF-001-2019), backward compatible with V1.1 and V1.0
  • Supports CXP-12 protocol, maximum high-speed link rate up to 12.5Gbps, low-speed link up to 41.6Mbps
  • Supports multiple CoaXPress lanes to meet scenarios with large data volume and high bandwidth transmission
  • Supports multiple video streams, capable of directly connecting multiple independent sensors or multi-channel imaging devices
  • Supports up to 4 parallel CoaXPress lanes to improve transmission efficiency
  • Control channel operations via simple local bus without CPU participation, reducing resource consumption
  • Highly configurable video stream interface, can directly connect to various imaging sensors without extra conversion
  • Built-in CRC-32 checksum module to ensure complete and reliable data transmission

Supported Devices

  • Supports all Xilinx FPGA families
  • Validated platforms: KC705, KCU105, ZCU102

Functional Block Diagram

Figure 1 Data Flow Diagram of CXP2.0 DEVICE FPGA IP

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