Hamamatsu C15550‑22UP Trigger Latency Test

— Latency Measurement from Trigger Signal to Frame Valid (FVAL)

Test Object: PCIe‑1004 CoaXPress Frame Grabber + Hamamatsu C15550‑22UP Camera

1 Overview

In a triggered imaging system, latency is defined as the time interval from the valid edge of the external trigger signal to the rising edge of the Frame Valid (hereinafter referred to as FVAL) signal output by the frame grabber. This latency determines the predictability of the camera exposure window relative to external events and serves as a key indicator for synchronous acquisition systems.

This report adopts the direct oscilloscope measurement method to measure the trigger latency of the PCIe‑1004 frame grabber paired with the Hamamatsu C15550‑22UP camera under different image resolutions, trigger frequencies and exposure‑time settings. Latency decomposition and calculation method for net latency (excluding exposure time) are provided.

2 Test Environment and Methodology

2.1 Test Equipment and Wiring

• Frame grabber: PCIe‑1004 CoaXPress frame grabber (installed in PCIe slot, driver and host‑side software work normally).
• Camera: Hamamatsu C15550‑22UP camera, default falling‑edge trigger mode, exposure time configurable via software.
• Trigger source: Square‑wave signal output by signal generator; amplitude 3.3 V, offset 1.65 V, duty cycle 50 %. Frequency is configured for each test group.
• Observation instrument: Digital oscilloscope. CH3 connects to trigger‑source signal; CH2 connects to GPIO TTL_0 output of frame grabber.
• Signal routing: Via GPIO configuration of PCIe‑1004, the internal FVAL signal constructed from CXP data stream inside frame grabber is routed to TTL_0 pin for physical output.

2.2 Measurement Principle and Oscilloscope Configuration

The camera works under falling‑edge trigger mode by default, meaning exposure starts on the falling edge of trigger signal. FVAL is pulled high by frame‑grabber FPGA once it parses the Start‑Of‑Frame (SOF) marker inside CoaXPress data stream. Therefore, measurement uses the falling edge of trigger signal as time starting point and rising edge of TTL_0 (FVAL) as ending point. The time difference between the two edges equals total latency for corresponding test group.

• Oscilloscope trigger setting: Trigger on falling edge of CH3, for square‑wave of amplitude 3.3 V, offset 1.65 V, 50 % duty‑cycle.
• Measurement method: Use oscilloscope to measure time interval from CH3 falling‑edge to CH2 rising‑edge.

Figure 1 Signal Connection Diagram

3 Origin and Construction of FVAL Frame‑Valid Signal

In this system, FVAL (Frame Valid) is NOT a physical signal directly output from camera. Instead, it is a frame‑valid level signal generated in real‑time by the FPGA of PCIe‑1004 frame grabber on receiver side (RX), based on Start‑Of‑Frame (SOF) and End‑Of‑Frame (EOF) markers embedded inside CoaXPress data stream. Its generation logic is listed below:

• CXP stream frame delimitation: Camera splits one image frame into multiple image‑data‑packets transmitted over high‑speed CXP serial link. Frame‑boundary control markers (K‑code / special header‑tail frame‑delimiting symbols) are inserted at frame boundaries. CXP deserialization and stream‑parsing logic inside frame grabber identifies these two markers.
• FVAL assertion: When RX logic parses SOF marker for current frame, FVAL is immediately set high, indicating valid image data of this frame starts to flow into frame grabber.
• FVAL hold: FVAL stays high during transmission of all data‑packets for this frame (including valid image rows and horizontal blanking). High‑level duration equals receiving time for one full frame, determined by total image rows and CXP link rate.
• FVAL de‑assertion: Upon parsing EOF marker, FVAL is pulled low to mark completion of frame reception. Meanwhile EOF triggers DMA tail‑processing and frame‑buffer pointer flip operation.

Essentially FVAL is level representation of frame receiving window spanning SOF to EOF: rising‑edge of FVAL corresponds to moment frame grabber receives SOF marker; falling‑edge corresponds to moment receiving EOF marker.

Important note: FVAL represents data‑receiving valid window, NOT camera exposure window. Exposure takes place before SOF arrival. Camera finishes exposure and row readout first, then packetizes and transmits image data. For this reason total latency naturally contains exposure‑time term.

4 Latency Composition

Total latency from trigger‑signal falling‑edge to FVAL rising‑edge can be decomposed into four components:

T_total = T_d + T_exp + T_r + T_f

Where T_exp is known user‑configurable quantity. Sum of T_d, T_r and T_f is net processing latency excluding exposure time, which reflects inherent real‑time performance of acquisition link:

T_net = T_total − T_exp ≈ T_d + T_r + T_f

Figure 2 Timing Diagram

5 Test Results

Groups 1‑13 are frame‑start latency data. For full detailed test results please refer to attached spreadsheet Latency_Test.xlsx.

6 Notes

• Oscilloscope trigger channel must align with actual trigger edge of camera (falling‑edge in this test). Wrong edge setting will introduce measurement deviation of half trigger period.
• Confirm TTL_0 output is configured as FVAL function with output direction enabled within PCIe‑1004 frame‑grabber IO routing; otherwise measured signal will be invalid.
• Oscilloscope reading resolution directly determines valid precision of net‑latency result: reading resolution of 0.01 ms only guarantees ±10 µs accuracy for net latency. For higher precision use nanosecond‑level oscilloscope‑cursor reading or frame timestamp statistics method.