Open-source FPGA UDP Protocol Stack with Complete Test

【Open‑Source】KU5P Full‑Hardware UDP Ethernet Loopback, 10G/25G/40G Shared Core, Clone‑and‑Build

Figure 1 KU5P FPGA board and optical module daughter‑card physical photo

Figure 2 KU5P FPGA board and optical module daughter‑card physical photo

Figure 3 KU5P FPGA board and optical module daughter‑card physical photo

Figure 4 Hardware test wiring environment

What it is

This is a hardware‑accelerated UDP/IP/Ethernet protocol stack example based on Xilinx Kintex UltraScale+ KU5P. The pipeline workflow: receive packet → parse → checksum validation → swap source/destination address on port 1234 → FIFO buffer → loopback transmit. Implemented in pure FPGA logic, intended for rapid high‑speed Ethernet link validation.

Tech Stack

• Hard MAC: xxv_ethernet (10G/25G BASE‑R), l_ethernet (40G BASE‑KR)
• Data interface: AXI‑Stream; For 40G, ethernet_adapter performs 256↔64‑bit width conversion and cross‑clock‑domain handling
• Clock sources: On‑board 200MHz LVDS + GT reference 156.25MHz. MMCM(clk_wiz_0) generates 100M/156.25M/390.625M
• Network parameters: IP 192.168.1.128, MAC 02:00:00:00:00:00, UDP port 1234
• RTL derived from verilog‑ethernet (MIT license)

Project Structure & Getting Started

• Three sub‑projects: xxvethernet_10g / xxvethernet_25g / ethernet_40g, sharing fpga_core.v + rtl/ + lib/
• build.bat under each tcl/ folder: auto‑detects local Vivado 2022.2 → runs create_project -dir prj to rebuild project (including RTL/XDC/IP)
• Only rebuild scripts are committed to repository. Vivado project and generated outputs are placed under tcl/prj/ and ignored by .gitignore, giving clean clone results
• Open tcl/prj//.xpr → Generate Bitstream → download via JTAG. Send UDP packets from PC to 192.168.1.128:1234 to observe loopback behavior
• KU5P board manual, FMC‑QSFP‑X2 daughter‑card manual and 10/25/40G test reports are available under doc/

Applications: High‑speed data acquisition link verification / low‑latency Ethernet acceleration research / FPGA Ethernet hard‑IP teaching / interoperability test for optical modules, fiber cables and switches.

Issues and pull requests are welcome. Feature requests for other boards or rates (including 100G) can be submitted.

🔗 Repository: https://github.com/Hello‑FPGA/FPGA_UDP