1 Introduction

CoaXPress (CXP) interface is currently the mainstream interface protocol for high-speed industrial cameras. With flexible wiring methods and GenICam compatibility, it is widely used in scientific research, semiconductor, medical, automation and other scenarios. At present, the implementation of CoaXPress protocol mainly relies on foreign manufacturers such as Xilinx, Intel and Microchip. Therefore, it is urgent to verify this protocol on domestic FPGAs. The main work of this paper is the verification of CoaXPress interface based on fully domestic FPGAs.

As localization replacement enters a deeper stage, FPGA, as the core hub of digital systems, the performance of its high-speed serial transceiver (GT/SerDes) directly determines the application of the system in communication, industrial vision, edge AI and other fields. This document provides a standardized and reproducible test verification guide using the GT module of domestic Efinix FPGA, focusing on verifying the actual capabilities of domestic autonomous FPGA chips in the high-speed image interface CoaXPress (CXP) protocol, providing reference for customers' hardware design and scheme selection. Different from traditional solutions of overseas manufacturers, this test system is completely based on Efinix's independently developed Quantum® architecture and Efinity® development platform, focusing on verifying the high-speed signal integrity of domestic chips, and providing support for the landing of domestic FPGAs in high-end application scenarios.

The Titanium series FPGA is a 16nm low-power, high-performance FPGA targeting mid-to-high-end application requirements. Based on the Quantum® computing architecture, it achieves a perfect balance between low power consumption and high performance, while having the advantages of high bandwidth and small size. The TJ375 series used in the test project supports 4-core hard-core RISC-V processors, 8-16 pairs of 16Gbps transceiver interfaces, 2.5G MIPI DPHY and 3.7G LPDDR4 controllers. It can be applied to video acquisition, video processing equipment, mid-end medical imaging equipment, security and high-end vision applications, as well as 4G/5G communication equipment and other fields. Benefiting from the Quantum® computing architecture, compared with traditional FPGAs, Efinix FPGAs have significant power consumption-performance-area advantages, and the combination of cores and various I/O interfaces can support a variety of applications.

1.1. Overview of CoaXPress

CoaXPress (CXP for short) refers to a camera data transmission standard using coaxial cables for interconnection, mainly used to replace the previous Camera Link protocol, and is commonly found in scientific cameras, industrial cameras, medical imaging, aerospace defense and other scenarios. Camera Link is no longer suitable for the ever-growing data bandwidth requirements due to cable form, transmission speed and other reasons. At present, the maximum speed of the 2.0 standard is 12.5Gbps per lane. In addition to transmitting image data, a single lane can also transmit low-speed control signals (41.6Mbps), and can also supply power to the camera using the cable, namely "Power-over-Coax", with a maximum length of a single cable up to 100m.

• The maximum line rate of a single coaxial cable is 12.5Gbps, and single or multiple cables can be used. For example, 4 cables can provide a maximum data rate of 50Gbps.
• Long cable lengths, such as up to 100m at 3.125 Gbps and up to 35m at 12.5Gbps.
• Data transmission has real-time and low-latency characteristics, and the latency is fixed.
• Precise real-time triggering characteristics, supporting trigger transmission through coaxial cables without additional communication cables.
• Flexible and reliable performance can be obtained by using standard coaxial cables, such as RG59 and RG6 specifications, RG6 is recommended.
• Easy integration features: images, control communication, and power supply can use the same cable, and the cable price is low.

CXP is a point-to-point scalable interface, and the physical medium between the device and the HOST is a 75Ω coaxial cable. Each CXP interface includes 1 MASTER connection and several optional extended SLAVE connections, each connection requires 1 coaxial cable. Usually, the device numbers these connections, with MASTER fixed at 0 and SLAVE extended interfaces incrementing in sequence.

Each connection includes the following functions:

• High-speed serial data (usually Device to Host downconnection), up to 12.5 Gbps.
• Low-speed serial data (usually Host to Device upconnection), up to 41.6 Mbps.
• Power supply function (Host to Device), up to 13W.

1.2. Overview of SerDes

SERDES is the abbreviation of English SERializer/DESerializer. It is a high-speed interconnection technology widely used in high-speed serial interfaces. This technology is a time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology. At the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, and after passing through the transmission medium (optical cable or copper wire), they are converted back into low-speed parallel signals at the receiving end. This point-to-point serial communication technology can fully utilize the channel capacity of the transmission medium, reduce the number of required transmission channels and device pins, increase signal transmission speed, and thus reduce communication costs. In the development process of transmission interfaces, serial interfaces mainly use differential signal transmission technology.

A general SERDES architecture mainly consists of the following modules:

1. Serializer: Acquires n-bit parallel data at a rate of y, then converts it into a serial data stream at a rate of n times y;
2. Deserializer: Acquires a serial data stream at a rate of n*y, and converts it into parallel data with a width of n at a rate of y;
3. Rx (Receive) Align: Aligns the input data to the appropriate word boundary. Several different mechanisms can be used, from automatic detection and alignment of a special reserved bit sequence (usually called Comma) to user-controlled bit slipping;
4. Clock Manager: Manages various clock requirements, including clock multiplication, clock division and clock recovery;
5. Transmit FIFO: Allows incoming user data to be stored before transmission;
6. Receive FIFO: Allows received data to be stored before deletion (data buffering); crucial in systems requiring clock correction;
7. Receive Line Interface: Analog receive circuits include differential receivers and may include active or passive equalization;
8. Transmit Line Interface: Analog transmit circuits usually allow different drive strengths. It can also allow pre-emphasis transmission;

The basic block diagram of the 8B/10B SERDES module is as follows:

A complete 8B/10B SERDES module: the Serializer consists of 8B/10B encoder, PRBS code generator, parallel-to-serial conversion circuit, differential signal transmitter, PLL and other modules; the Deserializer includes differential signal receiver, CDR (Clock and Data Recovery circuit), serial-to-parallel conversion circuit and 8B/10B decoder.

1.3. Overview of GT

Gigabit Transceiver (GT), the high-speed serial transceiver, is a general term used by FPGA manufacturers for the hard-core modules of high-speed serial transceivers integrated inside the chip. Its main function is to realize point-to-point high-speed serial data transmission, with typical line rates ranging from several hundred Mbps to over 100 Gbps. Compared with traditional parallel synchronous interfaces (which need to transmit data and clock simultaneously), GT adopts Clock and Data Recovery (CDR) and serialization technology, completely eliminating the rate bottleneck caused by clock skew and signal offset in parallel buses. A standard GT channel (Lane) is usually composed of two complementary sub-layers: PMA and PCS, both of which are physically hardened circuits and do not consume FPGA logic resources.

1. PMA (Physical Medium Attachment layer): Core functions include serial/parallel conversion (SerDes), transmit pre-emphasis or de-emphasis, receive Continuous Time Linear Equalization (CTLE) and Decision Feedback Equalization (DFE), clock generation and recovery (CDR).

2. PCS (Physical Coding Sublayer): Core functions include 8B/10B, 64B/66B encoding/decoding, channel bonding, clock correction and elastic buffer, PRBS testing.

PMA determines the maximum rate and transmission distance that GT can support; PCS determines the protocol format for framing and aligning data. Together, they realize the complete conversion from parallel data inside the FPGA to serial bit stream outside.

2 Hardware Description

The project mainly includes three modules: data transmission module TJ375N1156X, FMC to CXP module COAXPRESS 4T FMC (FMC-CXP-4T), and data acquisition module PCIe-1004. The Efinix TJ375N1156X development board is used to send data through the FMC B interface, the FMC-CXP-4T sub-card is inserted into the FMC B interface, and the CXP cable is used to transmit data to the PCIe-1004. The Efinix TJ375N1156X development board uses Lane1~4 of Quad2 to send four-channel data with a data bit width of 40 bits, and the transmission rate can be adjusted to 1.25Gbps, 3.125Gbps, 6.25Gbps, 10Gbps, 12.5Gbps.

2.1. Titanium Series TJ375 N1156X Development Board

The Titanium Series TJ375 N1156X Development Board is equipped with 4 SFP+ (10G) interfaces and 1 PCIe 4.0 x 4 interface. Two high-performance 512 Mbit SPI NOR Flash chips on the development board support SPI Active x1/x2/x4/x8 mode configuration mode, and can also store other user data, such as RISC-V firmware; one 8 GB eMMC can be used to store user data, or you can choose to read and write your own SD card using the SD card connector on the board. The development board is equipped with a highly integrated Ethernet RJ45 interface supporting RGMII with a maximum rate of 1000 Mbps. The Titanium Series TJ375 N1156X Development Board also has a USB to dual-channel JTAG chip, supporting FPGA loading and RISC-V SOC JTAG debugging. The development board is also equipped with 2 FMC (LPC) interfaces, each with 4 high-speed transceiver lanes. The board components are shown in the following figure:

The full-duplex transceivers of TJ375 FPGA support multiple protocols, including PCIe® Gen4 (data rate up to 16Gbps), Ethernet 10GBase-KR and Ethernet SGMII. PCIe and Ethernet transceivers have hard-core PCS, making protocol implementation and use easier. TJ375 also supports PMA Direct mode with data rates up to 12.5 Gbps, which can be used for custom protocols. In addition, 3 TJ375 hard-core MIPI TX and 3 TJ375 hard-core MIPI RX (each lane with a maximum rate of 2.5 Gbps respectively), 2 TJ375 soft-core MIPI TX/RX (configurable as LVDS or other standards with a maximum rate of 1.5 Gbps per lane) and 2 hard-core LPDDR4 and LPDDR4X controllers are provided.

The TJ375 high-speed transceiver interface is a multi-protocol, full-duplex transceiver supporting data rates from 1.25 Gbps to 16 Gbps. The TJ375 N1156X Development Board supports 10GBASE-R SFP+ interfaces.

Board Features:

• 2 x 8 Gbit (32 Mbit x 16 DQ x 8 bank x 2 channel) LPDDR4/LPDDR4X SDRAM: supports x32 data width, read/write speed up to 3.3 Gbps
• 4 SFP+ interfaces
• PCIe 4.0 x 4
• 2 LPC FMC interfaces (each FMC interface with 4 high-speed transceiver lanes)
• TJ375 PLL input supports 25 MHz, 33.3333 MHz, 74.25 MHz, 100 MHz and 156.25 MHz
• USB Type-C interface for configuring the development board and USB to JTAG chip

2.2. COAXPRESS 4T FMC (FMC-CXP-4T)

Chongqing Xingce Electronics' FMC-CXP-4T 4-channel CoaXPress FMC sub-card is suitable for any CXP image simulation and camera prototyping. The product supports up to 4-channel CXP-12, has an FMC HPC interface, and can be adapted to any FPGA board with an FMC HPC interface.

Main Features:

• Supports up to 4 CoaXPress links with a maximum rate of 12.5Gbps
• 4 x HD BNC connectors for high-speed CoaXPress data links, 1 SMA connector for link trigger input/output
• HPC connector – High Pin count connector, VITA 57.1 compliant
• Dimensions 63mm x 84mm, single-slot FMC
• Supports up to 12.5Gpbs rate, supports all nominal rates of CoaXPress 2.0 protocol, using high-speed PCB materials
• -40°C to 85°C operating temperature (industrial grade)
• On-board 2Kb EEPROM for writing user-specific information

2.3. PCIe-1004 4 Channel CoaXPress Frame Grabber

Chongqing Xingce Electronics' PCIe-1004 4 Channel CoaXPress Frame Grabber is a high-performance four-channel CoaXPress (CXP) image acquisition card specially designed for industrial imaging applications. The board supports the latest CoaXPress V2.0 standard, capable of transmitting high-speed image data and power (Power over CoaXPress, PoCXP) simultaneously through a single coaxial cable, simplifying system integration and wiring complexity. In addition, it provides rich external interfaces and internal expansion interfaces to meet various industrial automation needs.

The PCIe-1004 uses Xilinx Kintex UltraScale FPGA as the core processing unit, providing powerful real-time image preprocessing capabilities and flexible user logic expansion options. With up to 4GB DDR4 SDRAM on-board memory, it ensures smooth operation even in high frame rate and large data volume application scenarios.

Board Functions:

• Supports four independent CXP 2.0 inputs with up to 12.5Gbps bandwidth per channel;
• Built-in PoCXP function, supporting power supply to cameras through coaxial cables with a maximum power of 17W per channel;
• Provides Aravis SDK and GenTL Producer SDK, compatible with mainstream machine vision software platforms;
• Equipped with rich External I/O interfaces (such as RS-485, optocoupler isolated input/output, LVDS, TTL) for complex industrial environments.

3 Operation Instructions

1. Insert the PCIe-1004 into the PCIe slot of the PC and connect JTAG.
2. Connect the TJ375N1156X to the PC using the matching data cable.
3. Insert the FMC-CXP-4T into the FMC B slot of the TJ375 development board, and connect the 4T sub-card to the PCIe-1004 using CXP cables.

3.1. Driver Installation

To use the DEI60F225 series development board normally, configuring the hardware driver is a prerequisite. After the development board is connected to the computer through a USB cable, the PC side can recognize it correctly. Therefore, before powering on the development board and burning the program, we need to install the following driver configuration software. Hardware configuration: The PC side (under Windows environment) needs to install the Zadig tool.

1. Open Zadig, check List All Devices, then uncheck ignore Hubs or Composite Parents

2. Select interface1 of the corresponding device (the remaining interfaces are serial ports by default), select libusbk (v3.1.0.0)

3. Installation success display

If the development board still cannot be connected normally after the driver is installed successfully, check whether the CH340 serial port driver is installed on the host platform.

3.2. Test Process

After the development board is powered on, open the Efinix development software Efinity and open the sample project. Click the Open Debugger option in the menu bar, and select Debug in the Perspectives option.

The specific model of the connected development board can be seen in the right interface. Select the bit file to be burned in the Bitstream column and burn the file to the development board. After the burning is completed, the Device Status turns green, click the connection button shown in the figure to view the Debug signals.

After successfully connecting to the development board, click vio0 on the left to open the VIO data page. On this page, we can see key information such as init_done and clk_freq.

On the VIO interface, the rate switching function can be realized through the following operations:

First, enter the target rate in the rate column, then write 1 to rate_chg_trigger, user_phy_reset, restart_PU_rst, reset_tx_rx_pcs in sequence, and finally write 0 to the above four signals in sequence. You can judge whether the rate switching is successful through the init_done and clk_freq signals. The default rate after program download is 12.5Gbps, and the SerDes Width is configured as 40 by default. The reference rate result should be 12.5/40=0.3125, i.e., 312.5MHz.

You can use the GTKWAVE tool to view waveforms. The specific operations are as follows:

Click "Add trigger condition" in the la0 interface, select the signal you want to view in the pop-up dialog box, take the apb_done signal as an example, and click OK.

In the following interface, you can select the trigger condition, set the Value to 0 to 1 rising edge, click the RUN button after configuration, and wait for the signal.

When the condition is triggered, the GTKWave tool will pop up automatically, as shown below:

The target rate codes are shown in Table 3 below:

Start Vivado, click Open Hardware Manager, connect the PCIe-1004 to the PC, and import the .ltx file to update the ila data. Among them, the ext_phy_for_cxp_0_ext_phy_din signal in ila_2 is the data signal received by the acquisition card. You can judge whether there are errors in the data through the two signals ext_phy_for_cxp_0_ext_phy_cerr and ext_phy_for_cxp_0_ext_phy_perr. The cxp_host_0_ext_phy_speed signal is used to indicate the current rate. The relationship between rate and code is shown in Table 3 below:

3.3. Test Results

The following figures show the data received by the PCIe-1004 at different rates. The test data is 32'hb53c5cbc, and four-channel data is sent by Quad1.

In the above 5 tests, the data received by the four channels are all b53c5cbc, and no error data occurred.

3.4. Test Conclusion

Domestic Efinix FPGA is one of the few domestic FPGAs whose GT supports up to 12.5G or even 25G. CoaXPress and even CoaXPress over fiber can be ported to its FPGAs. Although its software ecosystem needs to be improved, it still provides a good choice for customers and the industry, and has great room for domestic replacement in the field of high-speed interfaces in the future.