FPGA DNA Retrieval

Basic Concepts of FPGA DNA

DNA is the unique identifier of an FPGA chip. Every FPGA has a distinct ID, known as Device DNA, which is equivalent to an ID card. This ID is permanently stored in the eFuse register of the FPGA chip during manufacturing and is unmodifiable. For Xilinx 7 series and earlier FPGAs, the ID is 57 bits in length, while for Xilinx UltraScale architecture, it is 96 bits.

Official Manual Description (7 Series):

The 7 series FPGA contains an embedded, 64-bit device identifier which is used to provide a 57-bit Device DNA value. The identifier is nonvolatile, permanently programmed by Xilinx into the FPGA, and is unchangeable making it tamper resistant. Each device is programmed with a 57-bit DNA value that is most often unique. However, up to 32 devices within the family can contain the same DNA value. The JTAG FUSE_DNA command can be used to read the entire 64-bit value that is always unique. Device DNA is composed of bits 0 to 56 of the 64-bit FUSE_DNA value. External applications can access the Device DNA or FUSE_DNA values through the JTAG port, and FPGA designs can access the DNA only through a Device DNA Access Port (DNA_PORT).

Key Interpretation:

In summary, JTAG can retrieve the 57-bit DNA_PORT and 64-bit FUSE_DNA. Up to 32 devices may share the same 57-bit DNA_PORT value, while the 64-bit FUSE_DNA is globally unique. When reading DNA through the FPGA resource area (logic design), only the 57-bit DNA_PORT is accessible, meaning you must use the 57-bit DNA_PORT for logic development.

How to Retrieve FPGA DNA

1. JTAG Debugging Retrieval

The complete DNA code of the chip can be directly viewed through the Vivado JTAG debugger, as shown in the following interface:

The DNA_PORT field in the interface is the 57-bit DNA code, which can be copied and saved directly.

2. Hardware Retrieval via Verilog Code (DNA_PORT Primitive)

The Xilinx official DNA_PORT primitive is used to serially read the 57-bit chip DNA in logic design. Reference Manual: 

https://fpga.eetrend.com/files-eetrend-xilinx/download/201408/7594-13761-ug4707seriesconfig.pdf

Example Verilog Code for Calling the Primitive:

DNA_PORT #(
    .SIM_DNA_VALUE(57'h123456789abcdef)  // Specifies a sample 57-bit DNA value for simulation
)
DNA_PORT_inst (
    .DOUT(dna_dout),   // 1-bit output: DNA output data.
    .CLK(sys_clk),     // 1-bit input: Clock input.
    .DIN(1'b0),       // 1-bit input: User data input pin.
    .READ(dna_read),  // 1-bit input: Active high load DNA, active low read input.
    .SHIFT(dna_shift) // 1-bit input: Active high shift enable input.
);
    

Comparison Interface of DNA Read by Logic and JTAG:

Official Reference Materials

Official Answer for JTAG DNA Retrieval: https://www.xilinx.com/support/answers/64178.html