Why Your FPGA IBERT Test Fails with Optical Modules

First, it's necessary to explain some optical module-related terminology. Make sure you understand the following terms before use

What is IBERT

IBERT (Integrated Bit Error Ratio Tester) is an integrated bit error rate testing tool provided by Xilinx/AMD inside FPGAs. It uses the GTH/GTY and other high-speed transceivers of FPGAs to generate and transmit PRBS pseudo-random sequences, while receiving and verifying data to count the Bit Error Rate (BER).

Functions of IBERT:

• Verify if the FPGA high-speed SerDes hardware link is normal (PCB traces, connectors, cables, optical modules)
• Adjust TX pre-emphasis/de-emphasis and RX equalizer parameters
• Measure Eye Diagram and Bit Error Rate (BER)
• No need to write any RTL code, can be used directly by generating IP in Vivado

PRBS Pseudo-Random Sequence Patterns

The test patterns used by IBERT are PRBS (Pseudo-Random Binary Sequence), generated by Linear Feedback Shift Registers (LFSR). The characteristics of PRBS sequences with different orders are as follows:

Key Difference Explanation

• Max Consecutive Identical Digits (CID): The maximum consecutive 0s or 1s of PRBS-N is N bits. Longer CID puts more pressure on the receiver's CDR (Clock Data Recovery), as long periods without transitions can cause CDR loss of lock.
• Longer sequence: The spectrum is closer to white noise, providing more comprehensive channel testing (covering more frequency components).
• PRBS-7: Short sequence, high transition density, friendly to CDR, easy to lock, suitable for initial debugging.
• PRBS-31: Extremely long sequence, maximum 31-bit consecutive identical digits pose the greatest challenge to CDR, making it the strictest pattern for channel quality assessment.

Which Pattern Should Be Used for Evaluation?

Practical advice: First use PRBS-7 to confirm basic link connectivity and CDR lock, then gradually upgrade to PRBS-31 for final evaluation. If PRBS-7 cannot lock, it indicates serious link issues (hardware failure or incorrect control signal configuration).

AOC DAC MPO SFP+ QSFP+ QSFP28 QSFP-DD

What Are the Differences in Usage Between AOC and DAC?

In terms of cables and PIN definitions:

In actual use, the high-speed SerDes differential pair electrical interfaces on the FPGA side are completely identical for DAC and AOC, with differences only in the cables themselves. Selection is mainly determined by transmission distance and wiring environment.

However, there are differences in the use of control signals (LPMode, ResetL, etc.):

Key Conclusion: Passive DAC has no internal electronic components, so control signals have no practical effect on it and no special processing is required on the FPGA side; while AOC and Active DAC contain active components such as lasers/TIAs inside, and LPMode and ResetL must be driven correctly, otherwise the module will not work properly.

QSFP28 Optical Module Usage

QSFP 1

QSFP28 Pin Layout

PIN Definitions are as follows:

If operation at 100G speed is required, the constraints for LPMODE, MODPRSL, RESETL, MODSELL, etc. are as follows:

Recommended Power-on Sequence:

1. After power-on, LPMode = High (low power), ResetL = Low (keep reset)
2. After power stabilization (≥100ms), release ResetL = High
3. Wait for module initialization to complete (detect IntL or wait 2s)
4. Read module information and configure parameters via I2C
5. Pull LPMode low to enter high power mode, 4 channels start normal transmission and reception

Hardware Design Note: As seen from the schematic, ModSelL, ResetL, ModPrsL, IntL, LPMode are all pulled up to QSPF_3V3 through 4.7KΩ resistors, complying with SFF-8636 specification requirements.

Therefore, in FPGA design for AOC or Active DAC, correct timing control of ResetL and LPMode must be noted; incorrect usage will cause the module to fail to work. There are no such constraints for Passive DAC.

Attached is the test on the Hello-FPGA-Z19EG development board, using 1 copper cable and 1 optical cable. The quality of the optical cable is significantly better than that of the copper cable https://imggrab.com/productinfo/257718.html

This is the eye diagram of the optical cable

Optical Cable Eye Diagram Test Result

This is the eye diagram of the copper cable

Copper Cable Eye Diagram Test Result

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Summary: Why Does Your FPGA Fail to Communicate with Optical Modules?

If your FPGA high-speed link works with DAC but fails with AOC, there is almost only one reason -- control signals are not driven correctly.

Core Check Items:

1. Is LPMode pulled low?
   Pull-up resistors will keep LPMode high by default (low power mode), at which time the laser does not work and optical power is zero. Must be actively pulled low by FPGA.
2. Is ResetL released correctly?
   Pull-up resistors will keep ResetL high by default (non-reset), but if the power-on sequence is incorrect, the module may not initialize properly. Should keep Low ≥ 2ms first, then High, wait 2s for initialization.
3. Why does Passive DAC work?
   Because Passive DAC is just a copper wire inside, without any electronic components -- no power-on, no reset, no power management required -- plug and play. While AOC contains lasers and TIA chips inside, which must be powered on and initialized according to specifications to work normally.

One-sentence summary: DAC working does not mean the link is problem-free, and AOC not working does not mean hardware failure -- check if your FPGA correctly controls LPMode and ResetL.